[LLHD] Fix misprint in llhd-desequentialize pass #7985
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AndreyVV-100
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maerhart
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maerhart
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Dec 13, 2024
| // CHECK: [[V0:%.+]] = llhd.prb [[CLK]] | ||
| // CHECK: [[V1:%.+]] = seq.to_clock [[V0]] | ||
| // CHECK: [[V2:%.+]] = comb.xor [[V0]], %true{{.*}} | ||
| // CHECK: [[V3:%.+]] = seq.compreg %false{{.*}}, [[V1]] reset [[V2]], %false{{.*}} |
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Note: this is currently incorrect as it should be an async reset, but seq.compreg does not support that (we need a register in the seq dialect that supports that without having the FIRRTL specific parts of firreg).
No need to change anything in this PR.
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maerhart
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Not yet. May you merge it? |
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Closes #7963